Clock Tree Structure Requirements
- Minimum Insertion Delay: A clock tree with minimum insertion delay will reduce clock tree power dissipation due to few clock tree buffers, uses less routing resources.
- Minimum skew: Minimum skew helps with hold timing closure. However, a tight skew requirement will lead to increase in clock insertion delay, which in turn leads to increase in the clock network power.
- More Common Paths: Having more common paths between launch and capture flop reduces the impact of OCV effects. The variations will cancel each other when the sinks share the same clock path to the root as any process-variation occurrence in that path affects both flops equally.
- Low Power Dissipation: A good clock tree structure should support implantation of clock gating to save the power.
Clock Tree Structure Types
- Conventional CTS
- CTS – Clock Tree MESH
- H – Tree
- Multisource CTS
Clock Distribution Challenges
Need to reduce the skew on distributing the clock
• This requires us to reduce the wire delay, and the buffer delay
– But we can’t reduce the delay to the required levels (sub 100ps) so
• Make the effective delay small, by balancing the delays of all the paths
– Change a total delay problem to a matching problem
– Make deltaT much smaller than Tdrive
Use a clock trees
• Match the delay on different branches of tree
– If the buffer delay matches
– If the wire delay matches
– Skew will zero
• Obvious question:
– How well can you match delays?
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