Synopsys Primetime Commands

Report All Violations

report_constraint –all_violators

Report Number Of Violations

The Number of Violations

Report Path Timing Reports

pt_shell> report_timing

Report Clock Network

report_clock_timing –type skew

Report Bottleneck Analysis (Identify cells involved in multiple violations)


Specify Timing Assertions

pt_shell> create_clock -name CLK -period 30 [get_port CLOCK] 

pt_shell> set_clock_uncertainty 0.5 [all_clocks] 

pt_shell> set_clock_latency -min 3.5 [get_clocks CLK] 

pt_shell> set_clock_latency -max 5.5 [get_clocks CLK] 

pt_shell> set_clock_transition -min 0.25 [get_clocks CLK] 

pt_shell> set_clock_transition -max 0.3 [get_clocks CLK]

Post layout clock tree

set_propagated_clock or 

set timing_all_clocks_propagated true

Similar Snippets

Synopsys Primetime Commands – vlsi

Synopsys Pocv Setup Commands – vlsi

Sta Multi Mode Multi Corner – vlsi

Clock Gating Check – vlsi

Difference Between Clock Buffer And Normal Buffer – vlsi

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