word2vec visualization

using vis.py ipython notebook version: https://gist.github.com/chezou/3899461aa550f73854a1 original vis.py https://github.com/nishio/mycorpus In [1]: import visword2vec # 単語で作ったモデル vis = visword2vec.visWord2Vec(“recipe_steps.bin”) # フレーズで作ったモデル vis_phrase = visword2vec.visWord2Vec(“recipe_steps-phrase.bin”) loading loaded loading loaded In [2]: def plot_both(word): vis.plot(word) vis_phrase.plot(word) In [3]: plot_both(‘チョコ’) [ 0.21099427 0.11427726] [ 0.19734898 0.13841781] In [4]: vis_phrase.plot(‘義理_チョコ’) [ 0.16700684 0.1221358 ] In [5]: plot_both(‘義理’) [ 0.17986007 0.14094272] [ 0.248188 0.16636363] In [6]: plot_both(‘あつあつ’)… Continue reading word2vec visualization

Unweighted test

Data too large for file format Data too large for file format source Similar Notebooks weighted kde deepsort with yolo kaggle sklearn competition solution auc derivation bayeslinear    


FMA: A Dataset For Music Analysis

Michaël Defferrard, Kirell Benzi, Pierre Vandergheynst, Xavier Bresson, EPFL LTS2. Free Music Archive web API All the data in the raw_*.csv tables was collected from the Free Music Archive public API. With this notebook, you can: reconstruct the original data, update some fields, e.g. the track listens (play count), augment the data with newer fields… Continue reading FMA: A Dataset For Music Analysis

What Is Hold Time

Hold time is defined as the minimum amount of time after the clock’s active edge during which data must be stable. Similar to setup time, each sequential element needs some time for data to remain stable after clock edge arrives to reliably capture data. This duration is known as hold time.The data that was launched… Continue reading What Is Hold Time


Synopsys Primetime Commands

Report All Violations report_constraint –all_violators Report Number Of Violations The Number of Violations Report Path Timing Reports pt_shell> report_timing Report Clock Network report_clock_timing –type skew Report Bottleneck Analysis (Identify cells involved in multiple violations) report_bottleneck Specify Timing Assertions pt_shell> create_clock -name CLK -period 30 [get_port CLOCK]  pt_shell> set_clock_uncertainty 0.5 [all_clocks]  pt_shell> set_clock_latency -min 3.5 [get_clocks… Continue reading Synopsys Primetime Commands

Synopsys Pocv Setup Commands

Location coordinates are required to calculate path distance but are not required to calculate the path depth. Set the read_parasitics_load_locations variable to true, and then use the read_parasitics command  pt_shell> set_app_var read_parasitics_load_locations truept_shell> read_parasitics Enable POCV Analysis – To enable graph-based POCV analysis, set the timing_pocvm_enable_analysis variable to true  pt_shell> set_app_var timing_pocvm_enable_analysis true  Set Standard… Continue reading Synopsys Pocv Setup Commands

Sta Multi Mode Multi Corner

What is MMMC MMMC stands for: Multi-Mode Multi Corner  What’s a Mode A mode is defined by a set of clocks, supply voltages, timing constraints, and libraries. It can also have annotation data, such as SDF or parasitics files. Many chip have multiple modes such as functional modes, test mode, sleep mode, and etc. What’s… Continue reading Sta Multi Mode Multi Corner

On Chip Variation Analysis

Variation Of Sources Causes of timing variations can include small variations in the way that features defined on a mask print on the surface of the chip because of the effect of surrounding features, variations in processes such as doping levels or etching that may remove more or less of a critical feature such as… Continue reading On Chip Variation Analysis

Mim Cap In Vlsi

Why MIMCAP is needed? The geometry scaling has led to thinner interconnects and reduced metal width. Interconnect lengths were also increased along with switching at gigahertz speeds to meet complex design requirement. The device scaling has increased the density of integrated transistors on the semiconductor wafer. There may be large current spikes due to simultaneous… Continue reading Mim Cap In Vlsi

Leakage Power

Leakage Power Power Consumption consists of Dynamic Power and static Leakage Power. In this blog, we will talk mainly about static Leakage power dissipation. Leakage Power depends upon… Gate length Oxide thickness Threshold voltage etc. Leakage Power can be divided in two parts… Leakage Power in stand by mode Leakage Power in active mode Static… Continue reading Leakage Power

Latch Based Designs

Latch Based Clocking • Every cycle is broken by two latches   – That means that each signal must go through two latches   – So if you set clocks up correctly, hold time should not be bad      • Problem is each latch has a different clock, so skew can causehold time issues• But in this system there… Continue reading Latch Based Designs